Seabright Technology Header Image

The ET-STM32 Stamp

A  STM32/Cortex-M3 based test board that brings a STM32F103RET6 out to a DIP package. The advantages are:

  • Cheap as
  • DIP pinout

The disadvantages are:

  • No JTAG so (at the moment) no debugging

See:

The device has a bootloader on UART1 which can be used to program the flash. In theory a GDB remote stub could be used as a monitor and allow basic debugging using the built in on chipdebug.

The board (see  http://www.futurlec.com/Pictures/ET_ARM_STAMP_II_600.jpg) brings out the following pins:

  • PA0 - PA15
  • PB0 - PB15
  • PC0 - PC13
  • PD2
  • RST, +3.3V, GND

It seems to be the 64 pin chip. USART1 is brought out via a MAX232 to a header. The boot mode and access to the bootloader is set by a jumper.

I'm interested in the UARTs. According to the datasheet they are available on:

  • PA2/PA3 - USART2
  • PB10/PB11 - USART3
  • PA8/PA9 - USART1
  • PC10/PC11 - UART4 or USART3 on remap
  • PC12/PD2 - UART5
  • PB6/PB7 - USART1

For some reason most are USARTS and UART4 is a UART.

CAN is on PA11/PA12 and PB8/PB9. USB is on PA11/PA12 only. JTAG is on PA13 (JTMS), PA14 (JTCK), PA15 (JTDI), PB3 (JTDO), and PB4 (NJTRST).

By fitting a trend line to Table 14 in the STM32 Datasheet, power consumption is 5.25 mA + 0.45 mA/MHz with peripherals off and 5.21 mA + 0.91 mA/MHz with peripherals on at the same frequency as the CPU. Note that you can clock down the peripherals to get a happy medium.