CircuitGear CGR-101 Internals
The CircuitGear is a PC based oscilloscope and function generator and, well, I couldn't resist opening mine up. Inside is a high speed dual channel ADC, a high speed DAC, a FPGA to drive it all, an ATMEGA48 for unknown use, and a FTDI UART-to-USB chip for the host communication.
The board is covered with test points which probably include the JTAG ports for the FPGA memory and the programming port for the ATMEGA.
The interesting chips are:
|FPGA||Xilinx XC3S50-4VQG100C||Spartan-3 FPGA (XC3S50 VQG100E is written on the part)||http://www.xilinx.com/support/#Spartan-3|
|FPGA code||Xilinx XCF01S||1Mbit 'Platform Flash' Programmable by JTAG||http://www.xilinx.com/products/config_mem/pf.htm|
|Op-amp||TI OPA4354A||250 MHz Quad Operational Amplifier||http://focus.ti.com/docs/prod/folders/print/opa4354.html|
|DAC||TI DAC908||8-Bit, 165MSPS DAC||http://focus.ti.com/docs/prod/folders/print/dac908.html|
|ADC||ADC10D020||Dual 10-Bit, 20MSPS, 150mW A/D Converter||http://www.national.com/pf/DC/ADC10D020.html|
|USB||FTDI FT232RL||USB UART IC - up to 3 Mbaud||http://www.ftdichip.com/Products/FT232R.htm|
|Microcontroller||Atmel ATMEGA48-20AU||Microcontroller with 4 k flash and 512 b RAM||http://www.atmel.com/dyn/products/product_card.asp?PN=ATmega48PA|
|I/O buffers||74LVT244A||3-state 3.3 V octal buffer/line drivers||http://www.nxp.com/pip/74LVT_LVTH244A_4.html|
|74HC4316M||Quad analogue switch|
The FPGA is driven by a 24 MHz crystal which is probably PLLed up in the chip. The ATMEGA is driven by a 18 MHz crystal. Apparently the UART runs at 230400 baud so it may not be hooked into the ATMEGA.
Using double speed mode on a 18 MHz clock the ATMEGA can acheive the following baud rates:
According to the FTDI datasheet:
Baud Rate = 3000000 / (n + x) where 'n' can be any integer between 2 and 16,384 ( = 2 ) and 'x' can be a sub-integer of the value 0, 0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not possible.
So the FTDI chip has a divide by eight fractional scaler. The rates that match up are:
At 10 bits/sample and running the UART at 1125000 we can transfer 90,000 samples/s. Using A-law or similar we might be able to do 112,500 samples/s. The current system doesn't pack the values so tops out at 11,520 samples/s.
Click on the image for the full size version.
PCB top side
- cgr-all-small.jpg (138.1 KB) - added by anonymous 8 months ago.
- cgr-right-small.jpg (240.9 KB) - added by anonymous 8 months ago.
- cgr-analogue-small.jpg (215.8 KB) - added by anonymous 8 months ago.
- cgr-overview.jpg (140.6 KB) - added by anonymous 8 months ago.
- cgr-all.jpg (2.1 MB) - added by anonymous 8 months ago.
- cgr-analogue.jpg (3.3 MB) - added by anonymous 8 months ago.
- cgr-right.jpg (3.7 MB) - added by anonymous 8 months ago.